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Renesas Electronics /R7FA6M3AH /GLCDC /BG_PERI

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Interpret as BG_PERI

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (FH)FH0 (FV)FV

FV=FV, FH=FH

Description

Background Plane Setting Free-Running Period Register

Fields

FH

Background plane horizontal synchronization signal period on the basis of pixel clock (PXCLK).

0 (FH): FH lines. The valid range is 0x017 to 0x3FF.
FV

Background plane vertical synchronization signal period on the basis of line.

0 (FV): FV lines.The valid range is 0x013 to 0x3FF.

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data